This antilog circuit design concept has been a very interesting but also strange development. Some key changes were made based on the previous Single Power Supply Stable Antilog Generator. These included a really good suggestion made on a Mod Wiggler thread to buffer the voltage between the PNP and NPN transistor so that the effect of the base current of the PNP transistor cannot take current from the NPN emitter current. This proved most providential, as it allowed true wide-range antilog results. The new update circuit design is shown in the Engineering Notes, below. Additional comments and some new discoveries now follow as well.
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| Engineering and Characterization Notes |
The circuit retains it's stable thermal properties. Because of complementary symmetry between matched PNP and NPN transistors, the antilog output is a thermally stable DC voltage.
Some new discoveries about operating mode were made though. The original design was intended to use matched opposite polarity transistors, where a +10.00V reference voltage at the emitter of the PNP antilog transistor would reflect to that same voltage at the base of the NPN transistor, due to a -Vbe (PNP) being matched within ±500µV to a complementary +Vbe. Then, using the LM324A adder-subtractor, to the +10.00V was imposed an attenuated V/OCT signal, nominally ±90mv, achieved from ±5V input voltage going through a calibrated attenuator for 18mV/volt.
The idea here being that a 50µA reference current in the NPN transistor emitter would set Vbe for the 0V input voltage: then up to +90mV of Vbe increase would cause 5 octaves of current increase (e.g. multiplication) in the antilog transistor; reciprocally, up to -90mV of Vbe decrease would cause 5 octaves of current decrease (e.g. division). But it never worked that way. The old circuit always had range problems, for which I fiddled with the reference current and the current-to-voltage gain resistor in the output op amp. Complicating results further was the increasing output linearization due to the output transistor base current going up for larger currents.
With that effect removed, a much wider range antilog was possible, but when using the full ±5V input voltage, above about +3V, the output would stop being antilog, and would have additional non-linear effects like jumps and also flatline; and it looked almost like a phase-reversal. Well, the reason became much clearer having the base current buffer in place. The up to +90mV side of the input was above the +10.00V Vbe reference, and the PNP transistor would start to be driven into cutoff!
So, the circuit was redesigned to provide a larger reference current that can be divided, and the input re-ranged to all-negative voltages of -10 ≤ Vi ≤ 0V. The idea being +10.00 - 180mV (e.g, one sided, or down-only). But it also turned out the the circuit can take some additional ΔV, and this does result in multiplication. The calibrated circuit produced -6.50V against a +7.50V reference voltage, with V/OCT characteristics. The top octaves represented some 6.5x current multiplication against the newly up sized NPN emitter reference current of 648.5µA (which sets a default Vbe, reflected as a -Vbe at the PNP transistor), for a peak output current of 4.22mA. For the lower octaves, the antilog transistor would instead divide the 648.5µA reference current.
What's super cool about this design is that other current ranges and current-to-voltage gains can be used. As well adjustments to the topology can be done to calibrate the range of the maximum output, while separately calibrating for octave response per 1V.
For example, the original idea of ±90mv Vbe change could be implemented by pre-setting the NPN reference current to a nominal "center" value, then the peak output current set by having an additional < 100mV offset of the ±90mv Vbe, so that it's preset to (10.00V - 90mV) for 0V Vi. Then the antilog transistor would be programmed to multiply (top octaves) and divide (bottom octaves) on a balanced basis. So, combine two effects: the setting of the Vi=0V Vbe value using the reference current, but then rather than adjust the value of the reference current to set the maximum output as a Vbe, instead just directly adjust the Vbe applied to the range of interest. For example: Iref × (2**5) ≝ Io|max (which then sets the output -ΔV, per the current-to-voltage gain resistor value).
With the "correct" antilog response finally possible, I turned more attention to why this circuit is thermally stable. Again, I don't have a thermal test chamber, but I can generate heat with a very bright flashlight, and this time I also used a 100mW laser for spot thermal generation. This antilog convertor has a robustly stable output in the face of thermal inputs.
My Theory Of Operation (TOO) is that the Vt change of the NPN and PNP transistors are complementary, so that if given a thermal gradient one transistor is multiplying the output current based on the Vbe, then by definition, if the other transistor is matched, and has the same Vbe, it must be dividing by the same amount because of opposite sign. This appears to be under logarithmic operation: summation of voltages that produce currents, but the Vt are of opposing signs. The results seen then are a logarithmic current multiplication/division for ΔVbe voltages, exactly what BJTs do well. The matched complementary BJT devices used in cascade is functionally similar to a log-antilog multiplier made with the same polarity of matched devices (which notionally does not need thermal compensation, as versus log-only or antilog-only use of the same matched transistors).
The LM324A op amp also has some odd anomalies, and I noticed a single small noise burst in the antilog output; and I had seen this too with the original circuit I tested (see the scope fotos, further below). And, when I looked at the actual transistor base signals, they seemed somewhat noisy, more so than using my scope at dramatically smaller voltage deflection levels (hence more scope voltage gain). All of these observational outcomes became most fortuitous toward explaining the TOO.
Because of the well-known cross-over distortion problem in the LM324A output stage, I thought maybe that was why I was seeing what looked approximately like a gaussian-shaped noise burst. So, I added a 15kΩ resistor to the output. Lo! The noise burst move "farther down" the antilog output ramp. But I decided to look at the noise burst more closely too: what this like a radio station leaking into my breadboard, or what?
And then I had the idea to test to if the noise changed qualitatively when adding heat to the THAT 340 transistor array. And it did! And then it hit me why this circuit works. Adding heat does increase the noise amplitude, but does not change the average DC level. What is happening is that at microvolt levels, thermally-induced multiplication and division is happening at megahertz frequencies, limited perhaps by the LM324A op amp unity gain crossover frequency. The Ft of the THAT 340 transistors is not matched between NPN and PNP, but it's generally > 300 MHz. The AC circuit response of the serially cascaded complementary transistors is causing thermal self-balance at random MHz rates, yielding a very steady DC voltage due to tight matching.
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Calibrated for 6.50V ΔV inverted against a Vref of 7.50V  |
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