Antilog DAC for V/KHz Response

I've had some recent successes using the TC9400 as an extremely accurate V/F convertor, in terms of linearity and calibrated dynamic range. In addition, in the early 2000's I was able to build a pickoff amplifier with the TC9400 that enabled using the natural charge balancing waveform as an output: a sawtooth. Between the pulse output, the square-wave output, and the sawtooth of the TC9400, any conventional VCO waveform can be generated. 

Additionally, because of the charge balancing V/F technique used, unlike most electronic music VCOs, the TC9400 does not have a need for high-frequency calibration to compensate for comparator and integrator delays as an increasing proportion of the high frequency waveform period, etc. Instead the TC9400 V/F control voltage response is ruler flat from 10 Hz to 10KHz. It has a linearity of 0.05%, which is approximately 11-bit grade (2048:1). The natural transfer function of this device, when programmed with appropriate capacitors, is precisely 1V per 1KHz. The device can otherwise have a 100 KHz full scale frequency range, but 10 KHz is plenty for musical pitch range.

This got me to thinking about V/KHz in general. As the TC9400 offered the rudiments of an extremely accurate VCO for electronic music, the next step was obtaining an accurate antilog control voltage scheme that could match the linearity and dynamic range, so as to enable equal-tempered scales for music. While I've developed various transistor-based antilog circuits over many years, a recent success with a trimless VCA motivated me to seek a new trimless and drift-free antilog DAC, rather than a pure analog antilog generator that requires temperature compensation. This would allow digital input for a VCO, direct from a keyboard or other controller. By changing a reference voltage, the VCO has flexible frequency, but the antilog DAC would allow precise frequency ratios for an equal tempered musical scale. Alternatively, a linear ADC in front of the antilog DAC would allow V/OCT analog input, while retaining the drift-free and musically accurate properties.

The circuit below is a 6-bit 5-octave plus (64 semitones) antilog DAC. It was an initial test circuit to see how well even (mostly...) ±5% resistors, CMOS switches, and op amp voltage followers could produce an antilog response. The circuit works by switching an attentuation of 2**(-n/12)*Vref, or +1*Vref, n being a power-of-two integer: 1, 2, 4, 8 ... Values of 1/n of the same sequence are also possible, which produce fractions of semitones. The upper 2 bits required 1% resistors, because the ratios needed could not be produced accurately with only a pair of 5% resistors in the EIA-24 series. A particular goal was to first confirm monotonic action, then see that good ratio accuracy results, even with EIA-24. Resistor tolerance effects were not part of this study, as that will be addressed in an updated circuit design using 0.1% tolerance resistors from the EIA-96 values.

The circuit only uses a +15V supply, and operation is not dependent on the absolute voltage value of the supply voltage. A +2.500V LM4040 voltage reference stands in for a VCO pitch knob, a simple voltage divider set somewhere between 0V and 10V. In the final circuit, a +10.00V LM4040 would be used, but the +2.500V reference was used here to allow critical examination of the more "musically useful" voltage ranges. For a precise 1V/KHz VCO, with 2.500V as the reference voltage, the antilog DAC is producing 64 semitones for pitches ≤ 2.500 KHz.

The circuit works as a cascade of simple multipliers, where each bit produces a twelfth-root-of-two attenuation of the voltage from a previous stage, or else 1.0 times that voltage. In the 6 stages, the values of n were programmed as {1, 2, 4, 8, 16, 32}. For test purposes, a 6-bit digital code sequence is created by using part of a CD4040 counter. This counter is a ripple counter, and was used for mere convenience.

6-bit Antilog DAC Circuit Design

The intitial test circuit already offered monotonic reponse, and fairly good ratio accuracy, despite only using several ±5% resistors and some ±1% resistors. This prototype was aimed at generally seeing how well the concept would work. 

Several key ideas went into this design. 

  1. All sources of error should be ≪ 0.6%, so that as a composite, any possible DC signal path has less than this amount of error in total. In V/KHz, this results in pitch accuracy that is below a Just Noticible Difference (JND) amount.
  2. The action of each bit would be completely separate, so as to not affect other weightings. There are alternative resistor ladder circuit designs that could integrate two bits of response per stage, or even more. But this seemed problematic for the eventually desired extreme precision, because of the interactions. The isolation between stages is provided by op amp voltage followers. So, in this topology, more stages are required.
  3. The switching action is to be directed by inexpensive CMOS switches (CD4053), but the effect of their Rds(on) over temperature is to have no effect whatsoever.
  4. Because a SPDT switch action is used to select between 1x and attenuated voltages, convenience is offered for digital codes by performing bit-inversion with how the switches are wired. This avoids having to invert each bit of the digital code presented to the DAC, in order to have a code sequence that causes increasing antilog voltages with increasing code values. As wired, the test circuit provides 2**(-63/12)*2.500V for code 000000, and 1.0*2.5000V for code 111111.
  5. In particular to avoid DC error due to accumulating op amp offset voltages, extremely precise op amps are used. The TC913BCPA devices are use here, because they auto-calibrate out internal offset voltage and are well-suited for low-value DC voltages. The maximum offset voltage of this dual op amp is is ±30µV. In a longer cascade of 6-10 stages, the cummulative voltage offset if it were absolute worst case for all stages is still a very small fraction of the control voltage for a reference pitch like A4. At 440 Hz, this pitch is represented by a 440 mV control voltage in V/KHz. For the 6-stage test circuit, the worst case cummulative voltage offset error is significantly less then 0.6% of 440 mV: 6 * |±30µV| ≪ (0.006 * 440 mV). This error declines with higher pitches, and is still less then JND for lower pitches. Furthermore, op amp offset voltage distributions tend toward Gaussian, so it's highly unlikely that 6-10 op amps will have their worst-case voltage offset. The offset voltage of each individual op amp is far more likely to be a nominal that is < |±30µV|.

The ultimate goal is to expand the number of bits for greater resolution (e.g. fractions of semitones), and then to upgrade the attenuation ratio tolerance by using 0.1% resistors, with a small-valued 1% resistor to guardband the |±0.1%| tolerance of the primary attenuation resistors. This should result in a antilog DAC with extremely high musical scale accuracy, when driving a precision V/KHz VCO.

The following scope fotos show the characteristics of the antilog DAC. And a picture of the solderless breadboard implementation follows the fotos.

Overall Transfer Function with Vref = 2.500V

Last Octave, 1.25V to 2.50

Second-to-Last Octave

First Octave, with Vref = 2.500V 


Breadboard Implementation





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