Antilog Generator Test Circuit

Enginering notebook with Antilog Test Circuit.

I am now getting back into circuit development to allow full system design of the Model III EMS as a system. The emphasis is to use whatever precision linear components it takes to obtain the desired implementation results, in part because the typically necessary devices have already been acquired years ago -- so they are a sunk cost. Might as well use them.

Superstrip breadboard implementation of antilog generator. 

I first wanted to test an improved variant of a 1V/OCT antilog generator circuit that I tested almost exactly a 4 years ago, on May 8, 2016. This will form a more-or-less standard front end circuit for a variety of EMS functions.

This antilog generator does the usual tricks of thermal coupling a 1K +3300ppm thermistor to a LM394CH matched transistor pair. It's extremely stable. I've worked on a lot of antilog circuits, and you can immediately tell when thermal feedback is working well. This breadboard circuit does not even have the thermistor and precision transistor pair completely thermally connected - and yet it still works well to provide thermal stability.

For test development, a positive sawtooth control voltage ranging from 0.0V to 5.0V is input from a HP33120A function generator. This control voltage is is transformed into 0.0 to -10V internal control voltage, using an auxilliary op amp with a precision gain of 2x. The voltage translation is done to allow certain offset voltage limitations with the function generator to be circumvented.

The auxiallary op amp mimics an input circuit that would really be an precision voltage adder with a gain of -1x, thus matching 1V/OCT requirement.

The internal control voltage is attenuated so as to provide a ∆Vbe of approximately 180mv for 10V span of input, to match octave doubling for every 1V ∆V of control voltage input. For extremely precise octave interval tuning, the 5K trimmer probably needs to be a multi-turn device. A pair of 1.00MΩ resistors were used to generate a 5µA reference current for the matched transistor pair at a ∆Vbe of 0V. A pair of precision resistors were used because a 2.00MΩ precision resistor is harder to obtain. This limitation also afforded the use of an additional noise-reducing 0.1µF decoupling capacitor between the two resistors.

Some illustrative scope fotos follow.

Main I/O characteristics, Vi at ½ FS (for HP33120A Vos limitations).

I/O expanded with Vi emulating 8V FS (to allow 8 DIV display) and cursor showing 1V/octave division.

Several sweeps at FS.